Silicon carbide (SiC) is a high-hardness semiconductor material with a greater bandgap than silicon (Si), and has been used extensively in various types of semiconductor devices including power elements, hostile-environment elements, high temperature operating elements, and radio frequency elements. Among other things, the application of SiC to power elements such as switching elements and rectifiers has attracted a lot of attention. This is because a power element that uses SiC can significantly reduce the power loss compared to a Si power element.
Among various power elements that use SiC, a MOSFET is known as a typical switching element. Such a switching element can switch between ON state in which drain current of several amperes (A) or more flows and OFF state in which the drain current becomes zero by changing the voltages applied to its gate electrode. Also, in the OFF state, SiC will achieve as high a breakdown voltage as several hundred volt or more.
The structures of such a switching element that uses SiC are proposed in Patent Document No. 1 and Non-Patent Document No. 1, for example. Hereinafter, the structure of vertical MOSFETs proposed in those documents will be described with reference to the accompanying drawings.
FIG. 38 is a schematic cross-sectional view illustrating a unit cell 1000 of a vertical MOSFET that uses SiC. It should be noted that a vertical MOSFET typically has a plurality of unit cells. It should be noted that in FIG. 38, the sizes of the respective members are not to scale in the thickness direction. For example, the substrate 101 and the semiconductor layer 102 are reduced in the thickness direction using waves.
The unit cell 1000 of the vertical MOSFET includes a silicon carbide epitaxial layer 120 that has been formed on the principal surface of an n-type SiC substrate 101 with low resistivity, a channel layer 106 that has been formed on the silicon carbide epitaxial layer 120, a gate electrode 108 that is arranged over the channel layer 106 with a gate insulating film 107 interposed between them, a source electrode 109 that contacts with the surface 120s of the silicon carbide epitaxial layer, and drain electrode 110 arranged on the back surface of the SiC substrate 101.
The silicon carbide epitaxial layer 120 has a well region 103, of which the conductivity type (i.e., p-type in this example) is different from that of the SiC substrate 101, and a drift region 102, which is the rest of the silicon carbide epitaxial layer 120 other than the well region 103. More specifically, the drift region 102 is an n−-type silicon carbide layer including an n-type dopant, of which the concentration is lower than in the SiC substrate 101.
Inside the well region 103, defined are an n-type heavily doped source region 104 including an n-type dopant and a p+-type contact region 105 that includes a p-type dopant at a higher concentration than the well region 103. The well region 103, the source region 104 and the contact region 105 are defined by performing the process step of implanting dopants into the silicon carbide epitaxial layer 120 and a high-temperature heat treatment process step (i.e., activating annealing process step) that activates the dopants that have been introduced into the silicon carbide epitaxial layer 120.
The source region 104 and the drift region 102 are electrically connected together through the channel layer 106, which may be a 4H—SiC layer that has been formed on the silicon carbide epitaxial layer 102 by epitaxy process, for example. Also, the contact region 105 and the source region 104 make ohmic contact with the source electrode 109. Consequently, the well region 103 is electrically connected to the source electrode 109 via the contact region 105.
The source electrode 109 can be formed by depositing a conductive material such as Ni on the source region 104 and the contact region 105 of the silicon carbide epitaxial layer 120 and then annealing the material at a high temperature.
The gate insulating film 107 may be a thermal oxide film (i.e., SiO2 film) that has been formed by heating and oxidizing the surface of the channel layer 106, for example. The gate electrode 108 may be made of electrically conductive polysilicon, for example.
The gate electrode 108 is covered with an interlevel dielectric film 111 with a hole 113. Through this hole 113, the source electrode 109 of each unit cell is connected in parallel to an upper interconnect electrode (e.g., an Al electrode) 112.
In a MOSFET including the unit cell 1000 with the structure shown in FIG. 38, the source electrode 109 should make ohmic contact with the source region 104, which is an n-type semiconductor region, and with the contact region 105, which is a p-type semiconductor region, as described above. The reason will be described below.
In this MOSFET, current can be produced in the channel layer 106 that is located under the gate electrode 108 by applying a voltage to the gate electrode 108. Thus, current originating from the drain electrode 110 (i.e., drain current) flows through the SiC substrate 101, the drift region 102, the channel layer 106 and the source region 104 into the source electrode 109 (in ON state).
In this case, if the contact resistance between the source region 104 and the source electrode 109 were too high, then the resistance in the ON state (i.e., ON-state resistance) would increase too much to make a sufficient amount of drain current flow. That is why the source region 104 and the source electrode 109 should have a sufficient contact area between them and should also make ohmic contact to have reduced contact resistance between them.
Such a MOSFET is often built in an electric circuit such as an inverter or a converter. An electric circuit with such a coil, however, will produce induced current during switching. For that reason, when the MOSFET is switched, that induced current may sometimes flow from the drain electrode 110 into the source electrode 110 by way of the contact region 105.
In that case, if the contact resistance between the source electrode 109 and the contact region 105 were high, a parasitic bipolar transistor, consisting of the source region 104, the well region 103 and the drift region 102, would be turned ON. Then, part of the induced current would flow instantaneously around the channel layer 106, thus possibly damaging the channel or gate portion of the MOSFET. That induced current could also delay switching of the MOSFET. For that reason, the source electrode 109 should have a sufficient area of contact with not only the source region 104 but also the contact region 105 and should make good ohmic contact with them.
To ensure a sufficient area of contact between the source electrode 109 and the source region 104 and between the source electrode 109 and the contact region 105, the source electrode 109, the source region 104 and the contact region 105 may be designed in the following manner.
Portion (a) of FIG. 39 is a schematic cross-sectional view illustrating the source electrode 109, the contact region 105 and the source region 104 of the unit cell 1000 shown in FIG. 38. Portion (b) of FIG. 39 is a plan view illustrating the surface 120s of the silicon carbide epitaxial layer, on which the surface 105s of the contact region 105, the surface 104s of the source region 104 and the lower surface (conductive surface) 109s of the source electrode 109 arranged on the surface 120s of the silicon carbide epitaxial layer are shown.
In the following description, the surface 105s of the contact region 105, the surface 104s of the source region 104 and the conductive surface 109s of the source electrode 109 will be simply referred to herein as “contact region's surface 105s”, “source region's surface 104s” and “conductive surface 109s”, respectively.
As shown in FIG. 18, on the surface 120s of the silicon carbide epitaxial layer, the contact region 105 is surrounded with the source region 104. The profiles of the source region's surface 104s and the contact region's surface 105s are both quadrangular. The conductive surface 109s of the source electrode 109 has a quadrangular shape, which is analogous in shape to, and bigger in size than, the contact region's surface 105s. 
The conductive surface 109s is arranged so as to cover the contact region's surface 105s. That is why the center portion of the conductive surface 109s is in contact with the contact region's surface 105s and the peripheral portion thereof is in contact with the source region's surface 104s. 
With such an arrangement, the conductive surface 109s and the source region 104 can have a sufficient area of contact between them. As a result, when the MOSFET is turned ON, electrons can flow from the conductive surface 109s of the source electrode 109 toward the entire surrounding surface 104s of the source region as indicated by the arrows 119. In addition, since the conductive surface 109s can also have a sufficient area of contact with the contact region 105, it is possible to prevent induced current from damaging the channel or gate portion.
In such a MOSFET, the source electrode 109 may be formed in the following manner.
First, a conductive material film of Ni, for example, is deposited on the silicon carbide epitaxial layer 120 in which the source region 104 and the contact region 105 have been defined. Next, the conductive material film is patterned by photolithographic process, thereby forming a conductive material layer.
In this process step, the alignment is done such that the lower surface of the conductive material layer to be the conductive surface 109s contacts with the source region's surface 104s and the contact region's surface 105s as already described with reference to portion (b) of FIG. 39.
Thereafter, a post-deposition annealing process is carried out normally at a high temperature of about 1,000° C., thereby obtaining a source electrode 109. According to this method, a reaction layer is formed in the interface between the conductive material layer and the source region 104 and between the conductive material layer and the contact region 105 as a result of the high-temperature annealing process. For that reason, the source electrode 109 thus obtained will have good ohmic property with respect to these regions 104 and 105.
As used herein, the “source electrode” may refer herein to either a conductive layer including the reaction layer that has been formed in that interface or only the reaction layer.
In the MOSFET shown in FIG. 38, the source electrode 109 is aligned with respect to the contact region 105 and the source region 104 in the silicon carbide epitaxial layer 102 by performing a photolithographic process as described above. Generally speaking, however, a size shift or a misalignment could occur in a photolithographic process.
Among these types of errors, the “size shift” refers to the deviation of the planar sizes of the source electrode 109 from its designed values and can be reduced by optimizing the sizes of a photomask for use in the photolithographic process or the exposure conditions thereof.
On the other hand, the “misalignment” refers to the deviation of the actual location of the source electrode 109 from the expected one due to the misalignment of the photomask with respect to the ideal location of a resist film. As long as a known exposure system is used, it is very difficult to avoid the misalignment perfectly. Specifically, a misalignment of about 1 to 2 μm is inevitable when a contact aligner is used and a misalignment of approximately 0.1 to 0.2 μm will be caused by the use of a stepper. To get the mask alignment done, an alignment key needs to be left on the upper surface of the semiconductor layer 120 or somewhere else. However, that alignment key could be deformed during a heat treatment or etching process while the device is being fabricated. In that case, the degree of misalignment could be significantly greater than the initially expected one. Specifically, even if a stepper is used, a misalignment of 0.5 μm or more could be caused.
If such a misalignment occurred in the photolithographic process to form the source electrode 109, then the conductive surface 109s of the source electrode 109 could not be arranged at the location shown in portion (b) of FIG. 39.
To overcome such a problem, Patent Document No. 2, which was filed by the applicant of the present application, proposed that such an increase in ON-state resistance due to the misalignment be reduced by controlling the shape of the surface of the conductor that contacts with the source and contact regions (i.e., the conductive surface) and the shapes of the source and contact regions at the surface of the semiconductor layer.